FIELD OF THE INVENTION
The present invention relates generally to the operation of system memory in a personal computer (PC) system. More particularly, this invention relates to a memory controller unit for controlling the refreshing of dynamic random access memory (DRAM) chips, which comprise the system memory. Still more particularly, the present invention relates to a DRAM refresh logic which enhances system performance by performing refresh cycles primarily when the memory bus is idle.
FIG. 1 is a block diagram of a prior art computer system 10 that comprises a microprocessor or central processing unit ("CPU") 12, a CPU local bus 14 coupled to the CPU 12 and to a memory controller unit (MCU) 16, and a local bus peripheral device 18 also coupled to the CPU local bus 14. A system memory 17 is shown coupled to the memory controller 16 through a memory bus 15. In addition, a PCI (peripheral component interconnect) standard bus 20 is coupled to the CPU local bus 14 through a PCI bus bridge 22. A PCI peripheral device 28 is shown coupled to the PCI bus 20. The PCI peripheral device 28 may comprise a PCI Master controller that is capable of asserting ownership of the PCI bus during PCI Master cycles.
The microprocessor 12 shown in FIG. 1 may comprise a model 80486 microprocessor, and the CPU local bus 14 could comprise an 80486-style local bus. Alternatively, the processor 12 may comprise a Pentium-compatible processor, or some other processor design. The CPU local bus 14 includes a set of data lines D31:0!, a set of address lines A31:0!, and a set of control lines (not specifically shown). While the data and address lines are shown as 32-bit busses, one skilled in the art will understand that other bus widths could be used. Details regarding the various bus cycles and protocols of the 80486 CPU local bus 14 are not discussed in detail herein, as they are well known by those in the art, and are available in numerous publications. CPU 12, memory controller 16 and PCI bus bridge 22 have traditionally been fabricated on separate integrated circuit chips. A recent trend in computer systems has developed, however, in which the CPU core is combined with a variety of peripheral devices on a single integrated processor chip. An exemplary integrated processor chip includes a bus bridge that provides a high performance interface between an internal CPU local bus and an external PCI bus. By providing a high performance interface to an external PCI bus, relatively high performance characteristics can be achieved with respect to external data transfers.
The PCI bus bridge 22 provides a standard interface between the CPU local bus 14 and the PCI bus 20. As such, the PCI bus bridge 22 orchestrates the transfer of data, address, and control signals between the two buses. PCI bus 20 typically comprises a high performance peripheral bus that includes multiplexed data/address lines, and which supports burst-mode data transfers.
As noted, the PCI peripheral device 28 may comprise a PCI Master controller. In accordance with conventional techniques, the PCI Master may request "ownership" of the PCI bus, so that it can control transactions on the PCI bus 20. As one skilled in the art will understand, a plurality of PCI Masters may be included in the computer system, any of which may request ownership of the PCI bus 20. The PCI Master submits its request for ownership of the PCI bus 20 to the PCI bridge 22 on a control line in the PCI bus 20. The PCI bus bridge 22 typically arbitrates ownership requests among the various PCI Masters, and among the internal masters such as the CPU 12, and other internal masters. A priority ranking may be assigned to each of the various Masters to assist the bus bridge 22 in its priority determination.
The system memory typically includes banks of dynamic random access memory (DRAM) circuits. The DRAM connects to the MCU 16 via a memory bus 15, comprised of memory address lines, memory data lines, and various control lines. The DRAM banks, according to normal convention, comprises the working memory of the integrated processor. Data generally is transferred between DRAM 17 and other components in a computer system in two steps.
First, the accessing component generates signals on the address bus representing the row address of the desired memory location, which are latched into the DRAM when the row address strobe (RAS) signal is asserted low. At the next, or at subsequent, clock cycles, the memory device latches in the column address signal when the column address strobe (CAS) is asserted low. During an early write transaction, data is written into memory on the falling edge of the CAS signal while WE is active. In a read cycle, data from the selected memory cell is driven onto the data output line shortly after the assertion of the CAS signal while WE is inactive.
The speed of memory circuits is based upon two timing parameters. The first parameter is memory access time, which is the minimum time required by the memory circuit to set up a memory address and produce or capture data on or from the data bus. The second parameter is the memory cycle time, which is the minimum time required between two consecutive accesses to the memory circuit. For DRAM circuits, the cycle time typically is approximately twice the access time. DRAM circuits general have an access time in the approximate range of 60-100 nanoseconds, with cycle times of 120-200 nanoseconds. The extra time required for consecutive memory accesses in a DRAM circuit is necessary because the internal memory circuits require additional time to recharge (or "precharge") to accurately produce data signals. Thus, a microprocessor running at 10 MHz cannot execute two memory accesses, in immediate succession (or in adjacent clock pulses), to the same 100 nanosecond DRAM chip, despite the fact that a clock pulse in such a microprocessor is generated every 100 nanoseconds. Typically, the memory controller unit ("MCU") functions to regulate accesses to the DRAM main memory.
Because of these limitations, memory constructed with DRAM circuits is not always capable of responding to memory accesses within the time interval allotted by the central processing unit ("CPU"). In this event, external circuitry must signal to the CPU that supplementary processor cycles, or wait states, are necessary before the data is ready on the data bus, or before data from the data bus has been stored by the memory circuits. In addition to slowing the processing of the CPU, wait states generally require use of the CPU local bus, thereby limiting access to the bus by other system circuitry.
In addition to the delays caused by access and cycle times, DRAM devices are inherently dynamic devices which require periodic refresh cycles to protect the integrity of the stored data. These cycles consume a significant portion of the time available for memory accesses, and typically are required approximately every 4 milliseconds. If the DRAM circuit is not refreshed periodically, the data stored in the DRAM circuit will be lost.
Most industry standard DRAM devices have 256 rows. All of these rows must be refreshed once every 4 milliseconds, requiring refresh cycles to be run every 16 microseconds to complete the 256 refresh cycles in 4 milliseconds. In addition, system memory typically includes a plurality of DRAM banks. It has become increasing common to have the memory sub-system in a personal computer system support four or more banks of DRAM devices. While some computer systems have attempted to refresh all of the available DRAM banks at one time, the power consumed in such a DRAM refresh may be excessive, especially in portable systems that are battery operated.
As a result, most computer systems stagger the refresh cycles for each DRAM bank due to power considerations. Thus, refresh cycles are run sequentially to each of the DRAM banks provided in the system memory, consuming even more of the available memory access time. As an example, for a 4 bank DRAM memory sub-system with 256 rows, a refresh cycle may be required every 4 microseconds to meet the 4 millisecond refresh rate for each line in each bank of DRAM. This brings the refresh overhead to approximately 5% of the available memory bandwidth. A system with more than 4 banks of DRAM has an even higher refresh overhead, leaving less of a bandwidth available for the processor to access system memory, and thus increasing the frequency of wait states for the processor.
As the operating speed of processors increases and as new generations of processors evolve, it is advantageous to minimize wait states to fully exploit the capabilities of these new processors obtaining the maximum benefit of these new generations of high speed processors in personal computers, however, is especially difficult, because of size and power limitations of other components in the system, such as the DRAM system memory. With memory intensive applications, such as those involving technical or scientific calculations or computer aided design programs, the memory access time can greatly reduce the system performance.